Frequency control for paralleled AC systems

ABSTRACT

A frequency control utilizing a reference oscillator and a signal controlled oscillator is disclosed. The frequency control maintains the frequency of an output signal at the same frequency as the reference oscillator if there is no signal present at a frequency control input. A signal at the frequency control input causes the frequency of the output signal to be varied accordingly. The frequency control contains a feedback loop which compares the output of the signal controlled oscillator with the fixed frequency of the output of the reference frequency oscillator. The frequency control of the present invention has particular applicability as a frequency control for parallel-connected AC systems.

The Government has rights in this invention pursuant to Contract No.F33615-74-C-2037 awarded by the Department of the Air Force.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to frequency control circuitsand methods and, more particularly, to frequency control of alternatingcurrent systems having individual reference oscillators. The presentinvention is applicable for matching the frequencies of parallelconnected alternating current generators, and for adjusting thefrequency of an AC motor in accordance with a frequency control signal.

The present invention has particular application in the field ofvariable speed constant frequency generator systems used in any aircraftenvironment. The present invention allows the generator systems to beconnected in parallel so as to generate output signals having afrequency which is the average of all the individual frequencies of thegenerator systems. The present invention may also be used to control theprime mover speed in conventional generating systems so as to adjustfrequency of the output of each machine when the outputs are connectedin parallel.

2. Description of the Prior Art

The phase lock loop is a commonly used method of frequency control. Insuch phase lock loop systems, a master oscillator sets the systemfrequency, and all individual machines are then phase shifted withrespect to this master oscillator in order to share the load. In thisconventional method, the system maintains the master frequency. Suchphase lock loop master oscillator systems work well during normaloperation of parallel generator systems.

A major disadvantage of phase lock loop master oscillator systems isthat if for any reason the master oscillator malfunctions, the entiresystem frequency will be lost. If this malfunction should occur ingenerator systems generating in parallel, such as a variable speedconstant frequency (VSCF) system, there must be some backup means forproviding a new master oscillator signal. When the master oscillatorfails, however, logic circuitry must be provided to decide which of theoscillators of the other parallel systems is to become the new masteroscillator for controlling the frequency of the entire parallelconnected system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates in block diagram form two generator systems of theVSCF type connected in parallel in accordance with the presentinvention.

FIG. 2 shows an embodiment of the circuitry of the load division andsynchronization circuit 12 of FIG. 1 which generates a control signalproportional to the circulating current present in the parallelconnected systems.

FIG. 3 presents a block diagram of a frequency control having areference oscillator and signal controlled oscillator.

FIG. 4 illustrates an embodiment of the frequency control circuit ofFIG. 3.

FIG. 5 shows another embodiment of the frequency control circuit of FIG.3 and includes an additional counter start pulse circuit.

FIGS. 6A and 6B plot the wave forms which occur at the various stages ofthe circuit shown in FIG. 4, with the vertical axis of each plotrepresenting amplitude and with the horizontal axis of each plotrepresenting time.

SUMMARY OF THE INVENTION

In order to control the frequency of each parallel AC system inaccordance with the average of all individual systems, the frequencycontrol of each system in accordance with the present invention isprovided with a signal control oscillator in addition to its referenceoscillator. When not in parallel, the signal controlled oscillator isforced to the same frequency as the reference oscillator. The output ofthe signal controlled oscillator is used to control the frequency of theAC system or generator.

When two or more systems are paralleled or synchronized, a controlsignal is provided to the signal controlled oscillator. A control loopis provided in accordance with the present invention to adjust thefrequency of the signal controlled oscillator up or down in accordancewith whether the signal controlled oscillator output is faster than orslower than the reference oscillator output.

The frequency control of the present invention can determine whether thesignal controlled oscillator output is faster or slower than thereference oscillator output. The absolute frequency difference betweenthese two signals is determined by means of a discriminator.

The frequency control of the present invention averages all of thenatural frequencies of the individual systems. Since none of theoscillators of the paralleled systems acts as a master oscillator, thereis no need for the present invention to select a new master oscillatorif one of these oscillators should fail. The parallel connected systemsin accordance with the present invention will automatically average thefrequencies of the remaining systems.

The present invention may also be used to adjust the frequency ofmotors. A reference oscillator maintains the nominal speed, and speedadjustment is accomplished using a second control signal applied to thefrequency control loop.

The actual determination of whether the reference oscillator or thevoltage controlled oscillator is faster or slower is determined in thepreferred embodiments by phase shifting the output of the referenceoscillator. The reference oscillator output and the phase shiftedreference oscillator output are each discriminated with respect to theoutput of the signal controlled oscillator. Determination of which ofthese signals is leading determines which oscillator has a higherfrequency.

DETAILED DESCRIPTION OF THE INVENTION

In FIG. 1, there are shown two generators connected in parallel whichutilize frequency controls in accordance with the present invention. Inthe system shown, the circulating currents between phase A of generator1 and phase A of generator 2 are detected. These circulating currentsalong with the reference oscillator associated with each generator arethen used to control the frequency of each generator. More specifically,with respect to generator 1, there is shown a current transformer 10connected to the phase A output, and a similar current transformer 11connected to the phase A output of generator 2. By means of atransformer control loop 17, the transformers 10 and 11 sense thecirculating current, and apply a voltage proportional to thiscirculating current to the load division and sync circuit 12.

The load division and sync circuit 12 generates a control signal, e.g.,a voltage, which is proportional to a phasor portion of the circulatingcurrent, and this control signal is applied via a line 20 to a frequencycontrol 13. For purposes of explanation, the control signal on line 20is referred to as a control voltage signal, but this control signalcould also be a control current signal. The frequency control 13 hasassociated with it reference oscillator 1, which is represented bycircuit block 13a. The frequency control 13 adjusts the controlledfrequency output on a line 14 in accordance with the referenceoscillator 13a and the control voltage on line 20. A wave generator 15,such as that which is used on a variable speed constant frequencygenerator of the type shown in U.S. Pat. No. 3,873,928, entitled"Reference Wave Generator Using Logic Circuitry for ProvidingSubstantially Sinusoidal Output," to David L. Lafuze, and assigned tothe General Electric Company, receives on line 14 the controlledfrequency signal from frequency control 13.

In the case of a VSCF system, such as that shown in U.S. Pat. No.3,902,073, entitled "Starter Generator Electrical System Utilizing PhaseControlled Rectifiers to Drive a Dynamo-Electric Machine as a BrushlessDC Motor in the Starter Mode and to Provide Frequency Conversion for aConstant Frequency Output in the Generating Mode," to David L. Lafuze,and assigned to the General Electric Company, it is known that theimpedance of the generator is at approximately 45° lagging or in theinductive direction. In the instance of a VSCF generator, the wavegenerator, such as wave generator 15, will produce a substantially 45°leading signal along with many other signals necessary for generatorcontrol and operation. This 45° leading signal is the reference signalon a line 16 which is fed back to the load division and sync circuit 12.This reference signal enables the load division and sync circuit 12 toproduce the control voltage signal on line 20 by selecting a phasorportion of the circulating current, the difference signal from thetransformer control loop 17.

Also shown in FIG. 1 are lines 18 and 19, which feed back to the loaddivision and sync circuit 12 the terminal voltages present at generator1 phase A and generator 2 phase A, respectively. These terminal voltagesare used in the initial synchronization of the two generators.Synchronization of the generators is initiated by a control switch 9,the closing of which activates a phase lock loop system within the loaddivision and sync circuit 12 and a phase lock loop system within itscounterpart for generator 2 for the purpose of bringing the generatorsinto approximate phase alignment. This generator synchronization isnecessary to prevent high transient currents which would otherwise occurwhen the contactor 21 is closed.

An identical control system in accordance with the present invention tothat used for phase A of generator 1 is shown in FIG. 1 for phase A ofgenerator 2. In structure, the two control systems are identical and,consequently, the system for phase A of generator 2 is not discussed indetail. In terms of operation, the circulating current signal derived bycurrent transformers 10 and 11 is of opposite polarity for the twocontrol systems. Thus, the control system for phase A of generator 2operates inversely to the operation of the control system for phase A ofgenerator 1. That is to say, if the control system for phase A ofgenerator 1 causes generator 1 to speed up, the control system for phaseA of generator 2 causes generator 2 to slow down correspondingly, andvice versa. It should also be understood that any number of generatorsystems can be controlled by control systems of the present invention inan analogous fashion so as to operate all of these systems in parallel.

In FIG. 2, there is shown in detail a load division and sync circuit 12which may be used for initial synchronization, and the production of thecontrol frequency signal for the frequency control 13. As stated above,there is a separate load division and sync circuit 12 associated witheach of the generators of the AC systems connected in parallel. Inoperation, the generators are synchronized, and once the synchronizationis complete, the contactors 21 are closed, causing the generators of thesystems to be operating in parallel. Upon the closing of the contactor21 (FIG. 1), the terminal voltages on feedback lines 18 and 19 areidentical because generators 1 and 2 are in parallel. Thus, the signalsat inputs 30 and 31 of the load division and sync circuit 12 of FIG. 2are identical so that the comparison signal, which is a function of thedifference between the signals at inputs 30 and 31 and which arenormally different during synchronization, goes to zero after closing ofcontactor 21. Thus, once contactor 21 is closed, the present inventioncontrols the parallel-connected systems in accordance with the voltagesignal for each phase of each generator, each voltage signal beingproportional to the circulating component in that phase of the totalparallel-connected system.

The top portion of FIG. 2 shows the synchronization circuit of the loaddivision and sync circuit 12 used for initial synchronization of the twogenerators, G1 and G2. Applied to inputs 30 and 31 are the terminalvoltages of phase A of generators 1 and 2, respectively, as thesegenerators are operating independently of each other. These terminalvoltage signals are fed through amplifiers 32 and 33 which convert thesetwo signals into square waves in accordance with their zero crossings.These square wave signals are supplied, respectively, to flip-flops 34and 35, which measure the phase difference between these two signals.When the square wave signal at the output of comparator 32 is leadingthe square wave signal at the output of comparator 33, the Q output offlip-flop 34 indicates this phase difference and is applied via ascaling resistor to the non-inverting input of an operational amplifier36 connected as a differential amplifier. Conversely, when the squarewave signal at the output of comparator 32 is lagging the square wavesignal at the output of comparator 33, the Q output of flip-flop 35indicates this phase difference and is applied via a scaling resistor tothe inverting input of operational amplifier 36. The output signal fromoperational amplifier 36 goes negative when generator 1 phase A leadsgenerator 2 phase A (which effectively causes the frequency of generator1 to be decreased) and goes positive when generator 1 phase A lagsgenerator 2 phase A (which effectively causes the frequency of generator1 to be increased.

The signal at the output of amplifier 36, which is the voltage controlsignal on line 20 of FIG. 1, is the output of a phase discriminator of aphase lock loop made up of the voltage controlled oscillator offrequency control 13, the wave generator 15 and generator 1. This phaselock loop brings the frequency and phase of phase A of generator 1 intoalignment with the frequency and phase of phase A of generator 2. Oncethis frequency and phase synchronization is achieved, contactor 21 isclosed, connecting generators 1 and 2 in parallel. Once the generatorsare in parallel, the phase discriminator made up of comparators 32 and33 and flip-flops 34 and 35 no longer provides a phase difference signalbecause the terminal voltage signals at the inputs of comparators 32 and33 are the same signal. Thereafter, the load division circuit shown inthe bottom part of FIG. 2 takes control of the frequency and phase ofthe generators by generating the control signal on line 20 proportionalto a component of the circulating current, which effectively adjusts thefrequency and phase of generator 1.

Referring now to the load division circuit of FIG. 2, a controltransformer loop designated generally by reference numeral 40 includes aprimary winding 43 of a transformer 41 and the secondaries of currentsensing transformers 42 and 42a and the burden resistors 50 and 50aconnected across secondaries 42 and 42a, respectively. Transformer 42provides at its secondary winding a signal proportional to the currentlevel of phase A of generator 1, and transformer 42a provides at itssecondary windings a signal proportional to the current level of phase Aof generator 2. The secondaries of transformers 42 and 42a are connectedas shown in the load division circuit of FIG. 2 to produce a differencesignal across burden resistor 50 proportional to the difference ofcurrents of the two generator phases A. This difference signal isapplied to the primary winding 43 of transformer 41, and a correspondingphase-inverted difference signal across burden resistor 50a is appliedto the primary winding 43a of an identical transformer 41a for phase Aof generator 2 (shown in dashed lines).

It should be understood at this point that only one load divisioncircuit is shown in FIG. 2 because it is assumed that generator 1 is asymmetrical, three-phase system with phases B and C being displaced 120°and 240°, respectively; therefore, if phase A of the total system iseffectively controlled, then phases B and C will be correspondinglycontrolled. However, if improved load division between theparallel-connected generators is desired, each phase of the total systemcan be measured and controlled using a similar load division circuit asthat shown in FIG. 2.

The purpose of transmission gates 45 and 46 connected to the respectivesecondary 44 leads of transformer 41 is to provide the system with phasesensitivity. Transmission gates 45 and 46 essentially act as on/offswitches, which are controlled by a reference signal on a line 48 (shownas line 16 on FIG. 1) from the wave generator 15. The purpose of thetransmission gates or discriminators 45 and 46 is to provide thatportion of the circulating current phasor which is used to control thefrequency of phase A of the total system.

In a normal generator system, when two generators are connected inparallel and the generated voltages are equal in amplitude but displacedin phase, i.e., a difference in frequency exists between the two, thephasor difference voltage of the two generated voltages is at 90° to thesystem terminal voltage. This phasor difference voltage applied to theinductive source impedance of the generators results in a circulatingcurrent in phase with the system terminal voltage. This circulatingcurrent signal is used by the present invention to control the speed ofthe generators and hence the frequency of the power produced thereby soas to reduce the circulating current to substantially zero.

In comparison, in a VSCF system, when two generators are connected inparallel and the generated voltages are equal in amplitude but displacedin phase, the phasor difference voltage of the two generated voltages isat 90° to the system terminal voltage. However, because the sourceimpedance of the VSCF is only 45° lagging, the circulating current isdisplaced from the phasor difference voltage by 45° as opposed to 90° inthe conventional generator system. This circulating current signal isthus displaced 45° from the system terminal voltage and is used by thepresent invention to control the frequency of the power generated by thecycloconverters so as to reduce the circulating current to substantiallyzero.

Referring again to FIG. 2, in the case of a VSCF system, the 45° leadingsignal on line 16 from wave generator 15 is brought in on line 48. Ifthe proper desired 45° leading signal cannot be furnished by wavegenerator 15, it may be generated by introducing a 45° phase lead to thephase A voltage from generator 1. In the case of a conventionalgenerator system, the signal applied to terminal 48 would be merely inphase with the system terminal voltage for phase A. The explanationgiven below for the load division circuit is for the VSCF application,but is equally applicable to the conventional generator application ifthe signal on line 48 is in phase with the system terminal voltage.

The control signal on line 48 is essentially a square wave, and is usedto switch the transmission gates 45 and 46. The transmission gates 45and 46 in conjunction with secondary winding 44 can be thought of asoperating similar to a full-wave rectifier controlled by the controlsignal on line 16 from the wave generator 15.

It is through the selection of one phasor part of the total differencecurrent signal of phase A that it is possible for the load divisioncircuit effectively to adjust the frequency of the power generated bythe cycloconverters. When two systems are connected in parallel (FIG.1), the frequency correction caused by the load division circuit in onesystem is in a first direction and the frequency correction produced inthe second system will be in the opposite direction. This frequencycorrection can be understood by assuming that the reference oscillatorsof the parallel-connected generator systems are different in frequency.If the reference oscillator 13a of generator 1 is lower in frequencythan the reference oscillator 13a' of generator 2, then the circulatingcurrent will tend to drive generator 1 to a greater frequency, while atthe same time tending to drive lower the frequency of generator 2.Inverter 47 merely acts to provide the inversion of the square wavesignal on input 48 applied to transmission gate 46 to produce thefull-wave phase discrimination action of the two transmission gates 45and 46.

Once the desired phasor portion of the circulating current has beenderived at the commonly connected outputs of transmission gates 45 and46, it is applied to an inverting input of an amplifier 49, which actsas a buffer stage. The output of amplifier 49 is supplied to theinverting input of amplifier 36 discussed above. The output of amplifier36 constitutes the frequency control voltage applied to frequencycontrol 13 to readjust the frequency of the electric power generated bythe cycloconverter of generator 1 phase A in accordance with theselected phasor portion of the circulating current. The output ofamplifier 36 is a DC signal having an amplitude proportional to theselected phasor portion.

FIG. 3 shows in block diagram form a preferred embodiment of thefrequency control 13. This embodiment is equally applicable to frequencycontrol 13'. Frequency control 13 includes a reference oscillator 60 anda voltage controlled oscillator 71. (Reference oscillator 60 isdesignated as block 13a in FIG. 1.) The signal supplied to a line 72 isthe output signal from amplifier 36 of the load division and synccircuit 13, and this signal is applied to the inverting input of anamplifier 70.

Within frequency control 13 is a control loop consisting of phase shift62, discriminators 62 and 63, filters 64 and 65, flip-flops 66 and 67,amplifier 70, voltage controlled oscillator 71, and a line 73. Thiscontrol loop in cooperation with the load division and sync circuit 12loop produces averaging of the frequencies of the reference oscillator60 and the corresponding reference oscillator of the other systemconnected in parallel. If the frequency control 13 is used in connectionwith a speed control of a motor, then a signal is applied to line 72which causes a readjustment of the frequency control loop of this speedcontrol.

The determination of any frequency difference between the voltagecontrol oscillator 71 and the reference oscillator 60 isstraightforward. This determination involves the use of a discriminator,such as discriminator 63, wherein the output of voltage controlledoscillator 71 is phase discriminated against the output of referenceoscillator 60. The output of discriminator 63 is a series of pulses, thefiltered average of which is indicative of any difference in frequency.For example, reference oscillator 60 produces a high frequency outputsignal having a fixed frequency in the 3 megahertz range.

There must be additional circuitry beyond that necessary to determinethe frequency difference in order to determine whether the frequency ofthe output of voltage controlled oscillator frequency 71 is less than orgreater than the output of reference oscillator 60. The relationship ofthe frequency of the output from voltage controlled oscillator 71 to thefrequency of the output from reference oscillator 60 is determined bythe present invention through the use of two discriminators as follows.One of the oscillators, in the case the voltage controlled oscillator71, is applied as an input to both discriminators 62 and 63, while theother oscillator, in this case reference oscillator 60, is applieddirectly as an input to discriminator 63 but is phase shifted by apreselected amount by phase shift 61 before being supplied as an inputto discriminator 62. The use of the phase shifting allows thedetermination of the frequency relationship between the two frequencysignals. That is to say, the phase of one of the discriminator outputenvelopes reverses with respect to the other discriminator outputenvelope when the frequency of the voltage controlled oscillator goesfrom being greater than to less than the frequency of the referenceoscillator. It should be noted that the phase shift produced by phaseshift 61 may be any amount, so long as it is not close to zero or 180°.A phase shift of 90° is easily obtainable with digital techniques, andis used in the preferred embodiments.

The outputs from discriminator 62 and the output from discriminator 63are filtered and squared by filters 64 and 65, respectively. Thisfiltering and squaring operation is necessary in order to obtainrespective square wave signals indicative of both the frequency and thephase relationship of the envelope outputs of discriminators 62 and 63.That is to say, the cycle time of either of the square waves isindicative of the absolute frequency difference between the outputs ofthe two oscillators, and the phase relationship between the two squarewaves is indicative of the actual frequency relationship between the twooscillator outputs. This analysis of the square waves is performed byflip-flops 66 and 67.

Flip-flops 66 and 67 are used to compare the square wave signals at theoutputs of filters 64 and 65 to establish the phase relationship betweenthese two square wave signals. The flip-flop having the square wave fromone of the filters applied to its data (D) input which goes positiveprior to the other square wave applied to its clock (CL) input istoggled and indicates that the square wave at its data input is leadingthe square wave at its clock input. The other flip-flop, however, iscross-connected and does not toggle because its data input is low whenthe square wave applied to its clock input goes high. Thus, the outputsof flip-flops 66 and 67 indicate the actual frequency relationshipbetween the two oscillator outputs.

The output of the toggled flip-flop is applied either to thenon-inverting or inverting terminal of amplifier 70, whose output drivesvoltage controlled oscillator 71 up or down in frequency depending onwhich of flip-flops 66 or 67 is toggled. For example, the output offlip-flop 66 is connected to the non-inverting input of amplifier 70,and the output of flip-flop 67 is connected to the inverting input ofamplifier 70. When flip-flop 66 is toggled, the output of amplifier 70goes positive, which indicates that the frequency of the referenceoscillator 60 is greater than the frequency of the voltage controlledoscillator 71. The toggling of flip-flop 67 indicates the oppositecondition.

As stated above, the toggling of either flip-flop 66 or 67 indicatesonly the direction of the frequency error and does not indicate thefrequency difference, which must be known. Either of the flip-flops 66or 67 is toggled for each cycle of the frequency difference. The outputsof flip-flops 66 and 67 are provided as inputs to an OR gate 68, whoseoutput goes high for each toggle. This output signal is applied to thereset (R) input of a counter 69, and allows counter 69 to count whenthis output signal is high. Counter 69 also has applied to its clock(CL) input the output signal from the reference oscillator 60.Therefore, counter 69 will count a given number of reference oscillatorcycles before the count is terminated by the output Q of counter 69going high, which resets flip-flop 66 or 67.

The average voltage at the Q outputs of either of the flip-flops 66 or67 is indicative of the frequency difference and is equal to theflip-flop high voltage times the ratio of the measured time divided bythe period of the difference frequency. The gain of the frequencydifference detector can be made as high as is desired by increasing thenumber of counts of counter 69. For example, if it is desired to controlthe output frequency to plus or minus 10% of the reference oscillatorfrequency, the following approach may be used. Counter 69 is set tocount eight frequency reference periods. When the high state of theflip-flops is 12 volts, a 10% frequency error will be indicated by a9.6-volt signal to the input of amplifier 70, which is eight divided byten times twelve.

Reference oscillator 60 is set to a high frequency value, for example, 3megahertz. By running reference ocillator 60 at a much higher frequencythan the generator output, the response of the frequency control loop israpid. The frequency control will introduce negligible phase shift inthe load division loop when, for example, the frequency of the generatoroutput is 400 Hz.

Referring now to FIG. 4, there is shown a detailed circuit of the firstembodiment of frequency control 13 of the present invention. In thisembodiment, the frequency of the output on line 74 from the voltagecontrolled oscillator is 3.06 megahertz when there is no control signalon line 72. The embodiment of FIG. 4 is constructed using CMOScomponents. CMOS components have been found to be advantageous in VSCFaicraft applications because of their low power consumption and highnoise immunity.

The reference oscillator consists of a 6.25 megahertz crystal 80,capacitors 81 and 82, resistors 83 and 84, and an inverter 85. Theoutput of the oscillator appears on line 86 and is applied to the clock(CL) terminal of a flip-flop 87. Flip-flop 87 produces at its Q outputthe logic state of its data (D) input when a clock input is received.Flip-flop 87 is a divide by two counter in that its D input is connectedto its Q output. The Q and Q outputs of flip-flop 87 are consequently at3.06 megahertz. Line 88 is connected to the Q output of flip-flop 87,and line 90 is connected to the Q output.

FIG. 6A plots the waveforms present at various points in the frequencycontrol circuit 13 of FIG. 4, with the vertical axis of each tracerepresenting amplitude and with the horizontal axis of each tracerepresenting time. The horizontal axis of each trace is consistent.

A flip-flop 92 is connected as a divide by two counter and produces atits Q output connected to a line 89 a signal whose frequency is one-halfof the frequency of the signal applied to its clock input from flip-flop87. The waveform of the output signal on line 89 is shown on FIG. 6A,and is a 1.53 megahertz square wave. This signal is applied to the Dterminal of a flip-flop 93 and to an input of an exclusive OR gate 94.Exclusive OR gate 94 produces the same function as discriminator 63 ofFIG. 3.

The 90° phase shift necessary for determining whether the voltagecontrolled oscillator is faster or slower than the reference oscillatoris produced by flip-flop 93. Line 90 is connected to its clock input.Flip-flop 93 produces at its Q output terminal a square wave signal thatis lagging by 90° the signal on line 89. The output signal on the Qterminal is applied via a line 91 to an input of an exclusive OR gate95. The waveform on line 91 is shown in FIG. 6A. Exclusive OR gate 95produces the same function as discriminator 62 of FIG. 3.

Both exclusive OR gates 94 and 95 have applied to their other inputs asignal on a line 97 representative of the voltage controlled oscillatoroutput. The frequency of the voltage controlled oscillator is 3.06megahertz. A flip-flop 96 is connected as a divide by two counter andhas its clock input connected to the output of the voltage controlledoscillator via a line 131. Hence, the frequency of the signal at the Qof flip-flop 96 is at 1.53 megahertz, and is applied via line 97 toexclusive OR gates 94 and 95.

For purposes of illustration, the signal on line 97 is first assumed tobe slightly lagging the signal on line 89, the reference oscillatorsignal, as shown in FIG. 6A. When this lag occurs, a series ofrelatively wide pulses appear on line 98, as labeled in FIG. 6A as line98 lag. Similar traces are shown for the state where the signal on line97 is leading the signal on line 89. The pulses from discriminators 95and 94 are of widths determined by the phase relationship between thevoltage controlled oscillator signal 97 and the reference oscillatorsignals 91 and 89, respectively.

The pulse train shown in FIG. 6B is representative of the outputs ofdiscriminators 95 and 94 and shows the condition where the frequencydifference is large, as shown by the fact that there are only a fewpulses per cycle of frequency difference. FIG. 6B plots the envelopes ofthe pulse trains that appear on lines 98 and 99 during such a condition.The curve marked "frequency difference" represents the output thatappears on line 99 since it is merely the voltage controlled oscillatoroutput discriminated against the reference oscillator output. The curvelabeled "VCO faster" is the envelope of the pulses that appear on line98 when the frequency of the VCO signal is higher than the frequency ofthe reference oscillator. Similarly, the curve marked "VCO slower" isthe envelope of the pulses that appear on line 98 when the frequency ofthe VCO is lower than the frequency of the reference oscillator. Acomparison of the signals on lines 98 and 99 determining whether thefrequency of the VCO is higher or lower than the frequency of thereference oscillator.

The transformation of the pulse trains at discriminator outputs 98 and99 to corresponding square waves is accomplished by a filtering andSchmitt triggering operation, as shown in FIG. 4. The filter, Schmitttrigger circuit which shapes the output signals on line 98 includes aresistor 101, a resistor 102, a capacitor 100, and an amplifier 103.Similarly, the output on line 99 is transformed to a correspondingsquare wave by the circuit comprising a resistor 105, a resistor 106, acapacitor 104, and an amplifier 107.

The waveform of the signal on line 109 is plotted in FIG. 6B. The signalon line 109 represents the absolute frequency difference. The operationof flip-flops 110 and 111, which correspond respectively to flip-flops66 and 67 of the embodiment of FIG. 3, is understood best if it isassumed that the signal on line 108 is leading the signal on line 109,as is shown in FIG. 6B. When this condition is present, the frequency ofthe VCO is higher than the frequency of the reference oscillator.

Referring again to FIG. 4, when the signal on line 108 leads the signalon line 109, flip-flop 110 always remain low because its clock (line108) goes high prior to when its data input (line 109) goes high.Conversely, flip-flop 111 will trigger once each cycle, and will triggeron the leading edge of the pulses on line 109 because its data input(line 108) is high at that time.

The outputs of flip-flops 110 and 111 when the signal on line 108 isleading the signal on line 109 are plotted in FIG. 6B. Similarly, theoutputs of flip-flops 110 and 111 when the signal on line 108 lags thesignal on line 109 are also plotted in FIG. 6B.

Connected to Q output of flip-flop 110 and Q output of flip-flop 111 arethe two inputs of an exclusive OR gate 112. Exclusive OR gate 112 isfunctionally equivalent to OR gate 68 of FIG. 3. The output of exclusiveOR gate 112 is high when either but not both the Q output of flip-flop111 is high or the Q output of flip-flop 110 is high. The output ofexclusive OR gate 112 is connected to the reset terminal of a counter113. The clock input of counter 113 is connected by a lead 90 to theoutput signal from the reference oscillator. The output Q of counter 113is fed back to the reset inputs of flip-flops 110 and 111. The number ofcounts of counter 113 specifies the periods that flip-flops 110 or 111remains in the Q high state. The Q output of flip-flop 110 is suppliedvia a line 114 to one of the inputs of an amplifier 116, and the Qoutput of flip-flop 111 is furnished via line 115 to the other input ofamplifier 116.

Also applied to the inverting input of amplifier 116 connected to line114 is the control voltage signal supplied via line 72 from the loaddivision and sync control circuit 12 of FIG. 2. A capacitor 121connected between the output and the inverting input of amplifier 116and a capacitor 120 connected between the non-inverting input and groundcause amplifier 116 to provide at its output a signal which is anintegral of the pulse train signals being provided at its inputs. Thisoutput signal from amplifier 116 is used to drive the voltage controlledoscillator.

The voltage controlled oscillator comprises NAND gates 124 and 125 andbuffer amplifiers 126, 127 and 128. The output of the voltage controlledoscillator appearing on line 74 has a center frequency of 3.06 megahertzwhen there is no signal on line 72, and this output signal is fed to thewave generator 15 of FIG. 1 for frequency control of the system.

In FIG. 5, another embodiment of the frequency control of the presentinvention is shown. The reference oscillator includes a multi-stagecounter 150 which divides the frequency of the basic oscillator andprovides at its Q2 and Q3 outputs frequency signals to the inputs of anexclusive OR gate 151. Exclusive OR gate 151 produces the phase shiftrequired for determining whether the frequency of the voltage controlledoscillator is higher or lower than the reference oscillator frequency.Thus, exclusive OR gate 151 produces the same function as flip-flop 93of FIG. 4. The inputs of an exclusive OR gate 152 are connected to theoutput of exclusive OR gate 151 and the output of the voltage controlledoscillator 180 on line 74. Exclusive OR gate 152 performs the samefunction as exclusive OR gate 95 of FIG. 4. The inputs of an exclusiveOR gate 153 are connected to the Q3 output of counter 150 and the outputof voltage controlled oscillator 180 and it performs the same functionas exclusive OR gate 94 of FIG. 4.

The filtering and squaring function is performed in the embodiment ofFIG. 5 by resistors 154 and 155, capacitors 156 and 157, and NAND gate158. NAND 158 includes an internal Schmitt trigger. These componentsproduce the same function as buffer amplifier 103 and its associatedcomponents in FIG. 4.

Resistors 159 and 160, capacitors 161 and 162 and NAND gate 163 performthe same filtering and squaring function for the output signal ofexclusive OR gate 153. These components thus produce the same functionas do buffer amplifier 107 and its associated components in FIG. 4.

Flip-flops 164 and 165 perform the same functions respectively asproduced by flip-flops 110 and 111 of FIG. 4. An exclusive OR gate 166produces the inverse function as produced by exclusive OR gate 112 ofFIG. 4, but because of the inversion produced by NAND gate 168, theoutput of NAND gate 168 is analogous to the output produced by exclusiveOR gate 112.

The embodiment of FIG. 5 also includes additional circuitry used toeliminate any ambiguity which occurs when the period of the count timeof the counter exceeds the period of the frequency difference betweenthe reference oscillator output and the output of the voltage controlledoscillator. If the count time of the embodiment of FIG. 4 exceeds thefrequency difference time, counter 113 will continue to count into thenext cycle. This interval overlap produces an ambiguity. As can be seenfrom the trace labeled flip-flop 111 (line 108 lead) of FIG. 6B, if theperiod of counter 113 extends into the period of the next count, theflip-flop 111 will not return to its reset state until after its clockpulse is received. When flip-flop 111 returns to its reset state, itwill go low and remain so until the next clock signal is received. Thus,when the period of the counter 113 exceeds the frequency difference, theoutput of flip-flop 111 will go low rather than remain at the properhigh level. The same ambiguity problem exists with respect to flip-flop110. In order to correct this ambiguity problem in the embodiment ofFIG. 4, additional circuitry has been added to the embodiment of FIG. 5.

NAND gates 167 and 168 and a capacitor 169 and a resistor 170 are theadditional circuitry added to the embodiment of FIG. 5 to prevent theambiguity condition. This circuit produces a negative-going transient atthe input of NAND gate 168 whenever the output of both NAND gates 158and 163 goes high. NAND gate 168 inverts the negative-going transient atits input. In this way, a positive transient is always applied to thereset input of counter 171 to restart its counting cycle. Thus, when thefrequency error is great, and the time period of counter 171 exceeds thetime period of the frequency difference, the Q outputs of flip-flops 164or 165 applied to the voltage control oscillator via amplifier 172 willremain at their high state rather than being reset to the low state forpart of every other frequency difference cycle.

In the embodiment of FIG. 5, amplifier 172 and its associated componentsperform the same function that is produced by amplifier 116 and itsassociated components of FIG. 4.

The voltage controlled oscillator of the embodiment of FIG. 5 isindicated by reference numeral 180.

It should be noted that the embodiments for implementing the apparatusand method of the present invention are only illustrative, and otherembodiments which produce the same function are included within thescope of this specification.

The apparatus of the present invention can be fabricated in discreetcomponent form, or it can be fabricated using any type of presentlyavailable integrated circuit technique including hybrid integratedcircuit technology. The apparatus and method of the present inventionare applicable for any VSCF power generation system of any phase,voltage level and preselected frequency, and for any conventional powergenerator or alternating current motor drive system.

What is claimed is:
 1. Apparatus for frequency adjusting an alternatingcurrent machine comprising:(a) a reference oscillator having an output;(b) a signal controlled oscillator for producing a controlled outputfrequency signal, having an input and an output effectively connected tosaid alternating current machine; (c) first means for producing a signalproportional to the frequency difference between said referenceoscillator output and said controlled output frequency; (d) second meansfor providing a signal indicative of whether said controlled outputfrequency is above or below the frequency of said reference oscillatoroutput; and (e) means for supplying a drive signal to said input of saidsignal controlled oscillator in response to said signal of said firstmeans and said signal of said second means.
 2. The apparatus of claim 1,wherein said first means comprises:(a) first discriminator means forfurnishing an output signal proportional to the phase difference betweensaid reference oscillator output and said controlled output frequencysignal; and (b) first filter means producing a filtered version of saidoutput signal of said first discriminator means.
 3. The apparatus ofclaim 2, wherein said second means comprises:(a) phase shift means forintroducing a desired phase shift to said reference oscillator output;(b) second discriminator means for supplying an output signal inputsconnected proportional to the phase difference between saidphase-shifted reference oscillator output and said controlled outputfrequency signal; (c) second filter means providing a filtered versionof said output signal of said second discriminator means; and (d) meansfor generating an output signal indicating the phase relationshipbetween said output signal of said first filter means and said outputsignal of said second filter means.
 4. The apparatus of claim 3, whereinsaid means for generating an output signal indicating the phaserelationship comprises:(a) a first flip-flop having a clock inputeffectively connected to said output signal of said first filter means,a data input effectively connected to said output of said second filtermeans, and an output; and (b) a second flip-flop having a clock inputeffectively connected to said output of said second filter means, a datainput effectively connected to said output of said first filter means,and an output.
 5. The apparatus of claim 4, wherein said means forsupplying a drive signal comprises:(a) an amplifier having inputseffectively connected to said outputs of said first and secondflip-flops, and an output effectively connected to said input of saidsignal controlled oscillator; (b) third logic means having inputseffectively connected to said outputs of said first and secondflip-flops, and an output; and (c) counter means having a reset inputeffectively connected to said output of said third logic means, a clockinput effectively connected to said reference oscillator output, and anoutput effectively connected to set or reset inputs of said flip-flops.6. An apparatus for producing a controlled frequency output,comprising:(a) a reference oscillator having an output; (b) phase shiftmeans for introducing a desired phase shift to said reference oscillatoroutput; (c) first discriminator means for providing an output signalproportional to the phase difference between said output of said phaseshift means and a signal present at an input; (d) second discriminatormeans for producing an output signal proportional to the phasedifference between said reference oscillator output and a signal presentat an input; (e) first filter means for furnishing a filtered version ofsaid output of said first discriminator means; (f) second filter meansfor supplying a filtered version of said output of said seconddiscriminator means; (g) first logic means having a clock inputeffectively connected to said output of said second filter means and aninput effectively connected to said output of said first filter means;(h) second logic means having a clock input effectively connected tosaid output of said first filter means and an input effectivelyconnected to said output of said second filter means; (i) third logicmeans having a first input effectively connected to said output of saidfirst logic means, a second input effectively connected to said outputof said second logic means, and an output; (j) counter means having areset input effectively connected to said output of said third logicmeans, a clock input effectively connected to said reference oscillatoroutput, and an output effectively connected to set or reset inputs ofsaid first and second logic means; (k) amplifier means having a firstinput effectively connected to said output of said first logic means, asecond input effectively connected to said output of said second means,and an output, (l) control signal input means effectively connected toone of said inputs of said amplifier means; and (m) a controlledoscillator having an input effectively connected to said output of saidamplifier means and having an output effectively connected to saidinputs of said first discriminator means and second discriminator means,said output providing a controlled frequency signal.
 7. The apparatus ofclaims 5 or 6, further comprising:(a) fourth logic means providing anoutput signal in a low state in response to said outputs of said firstand second filter means in a high state; (b) differentiator means forgenerating a derivative signal of said output of said fourth logicmeans; and (c) fifth logic means for providing a signal to said resetinput of said counter means in response to said output of said thirdlogic means and said derivative signal.
 8. A method of connecting andcontrolling alternating current systems having individual frequencycontrols with independent reference oscillators, comprising the stepsof:(a) connecting said alternating current systems for paralleledoperation; (b) measuring the circulating current between saidparallel-connected alternating current systems; (c) producing a firstcontrol signal proportional to a component of said circulating current;(d) Adjusting the individual frequency controls of each said alternatingcurrent system in accordance with said first control signal,includingapplying said control signal to a signal controlled oscillator;and simultaneously applying a second signal to said signal controlledoscillator having a magnitude proportional to the frequency differencebetween the output of said signal controlled oscillator and the outputof one of said reference oscillators, and having a polarity indicativeof the frequency relationship between said output of said signalcontrolled oscillator and said output of said one of said referenceoscillators; and (e) approximately synchronizing the frequency and phaseof said alternating current systems prior to connecting said systemstogether in accordance with step (a).
 9. The method of claim 8, whereinthe step of applying a second signal comprises the steps of:(a) phaseshifting said reference oscillator output; (b) discriminating said phaseshifted reference oscillator output and said output of said signalcontrolled oscillator; (c) discriminating said reference oscillatoroutput and said output of said signal controlled oscillator output todetermine the frequency difference between said reference oscillatoroutput and said output of said signal controlled oscillator; (d)filtering outputs from steps (b) and (c); (e) comparing said outputsfrom step (d) to establish which output of step (d) is leading; and (f)applying a signal to said signal controlled oscillator in accordancewith the output of steps (e) and (c).